UPSD33XX Datasheet, PDF (68/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 37. WDKEY: Watchdog Timer Key Register (SFR AEh, reset value 55h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDKEY[7:0]
Details
Bit
Symbol
R/W
Definition
[7:0]
WDKEY
55h disables the WDT from counting. 55h is automatically loaded in this
SFR after any reset condition, leaving the WDT disabled by default.
W
Any value other than 55h written to this SFR will enable the WDT, and
counting begins.
Table 38. WDRST: Watchdog Timer Reset Counter Register (SFR A6h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDRST[7:0]
Details
Bit
Symbol
R/W
Definition
[7:0]
WDRST
This SFR is the upper byte of the 24-bit WDT up-counter. Writing this
SFR sets the upper byte of the counter to the written value, and clears
W
the lower two bytes of the counter to 0000h.
Counting begins when WDKEY does not contain 55h.
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