UPSD33XX Datasheet, PDF (17/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
By default, the SRAM and CSIOP memories on
the PSD Module must always reside in data mem-
ory space and they are treated by the 8032 as
XDATA. However, the SRAM may optionally re-
side in program space in addition to data space if
it is desired to execute code from SRAM. The main
Flash and secondary Flash memories may reside
in program space, data space, or both.
These memory placement choices specified by
PSDsoft Express are programmed into non-vola-
tile sections of the uPSD33xx, and are active at
power-up and after reset. It is possible to override
these initial settings during runtime for In-Applica-
tion Programming (IAP).
Standard 8032 MCU architecture cannot write to
its own program memory space to prevent acci-
dental corruption of firmware. However, this be-
comes an obstacle in typical 8032 systems when
a remote update to firmware in Flash memory is
required using IAP. The PSD module provides a
solution for remote updates by allowing 8032 firm-
ware to temporarily “reclassify” Flash memory to
reside in data space during a remote update, then
returning Flash memory back to program space
when finished. See the VM Register (Table
78., page 143) in the PSD Module section of this
document for more details.
8032 MCU CORE PERFORMANCE ENHANCEMENTS
Before describing performance features of the
uPSD33xx, let us first look at standard 8032 archi-
tecture. The clock source for the 8032 MCU cre-
ates a basic unit of timing called a machine-cycle,
which is a period of 12 clocks for standard 8032
MCUs. The instruction set for traditional 8032
MCUs consists of 1, 2, and 3 byte instructions that
execute in different combinations of 1, 2, or 4 ma-
chine-cycles. For example, there are one-byte in-
structions that execute in one machine-cycle (12
clocks), one-byte instructions that execute in four
machine-cycles (48 clocks), two-byte, two-cycle
instructions (24 clocks), and so on. In addition,
standard 8032 architecture will fetch two bytes
from program memory on almost every machine-
cycle, regardless if it needs them or not (dummy
fetch). This means for one-byte, one-cycle instruc-
tions, the second byte is ignored. These one-byte,
one-cycle instructions account for half of the
8032's instructions (126 out of 255 opcodes).
There are inefficiencies due to wasted bus cycles
and idle bus times that can be eliminated.
The uPSD33xx 8032 MCU core offers increased
performance in a number of ways, while keeping
the exact same instruction set as the standard
8032 (all opcodes, the number of bytes per in-
struction, and the native number a machine-cycles
per instruction are identical to the original 8032).
The first way performance is boosted is by reduc-
ing the machine-cycle period to just 4 MCU clocks
as compared to 12 MCU clocks in a standard
8032. This shortened machine-cycle improves the
instruction rate for one-byte, one-cycle instruc-
tions by a factor of three (Figure 7., page 18) com-
pared to standard 8051 architectures, and
significantly improves performance of multiple-cy-
cle instruction types.
The example in Figure 7 shows a continuous exe-
cution stream of one-byte, one-cycle instructions.
The 5V uPSD33xx will yield 10 MIPS peak perfor-
mance in this case while operating at 40MHz clock
rate. In a typical application however, the effective
performance will be lower since programs do not
use only one-cycle instructions, but special tech-
niques are implemented in the uPSD33xx to keep
the effective MIPS rate as close as possible to the
peak MIPS rate at all times. This is accomplished
with an instruction Pre-Fetch Queue (PFQ) and a
Branch Cache (BC) as shown in Figure
8., page 18.
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