UPSD33XX Datasheet, PDF (12/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Port Pin
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
JTAGTMS
JTAGTCK
Signal
Name
TMS
TCK
80-Pin
No.
52-Pin
No.⁽¹⁾
In/Out
Basic
80
52
I/O General I/O port pin
78
51
I/O General I/O port pin
76
50
I/O General I/O port pin
74
49
I/O General I/O port pin
73
48
I/O General I/O port pin
71
46
I/O General I/O port pin
67
43
I/O General I/O port pin
66
42
I/O General I/O port pin
20
13
I JTAG pin (TMS)
16
12
I JTAG pin (TCK)
PC2
V_STBY
15
11
I/O General I/O port pin
PC3
TSTAT
14
10
I/O General I/O port pin
PC4
TERR
9
JTAGTDI
TDI
7
JTAGTDO TDO
6
PC7
5
7
I/O General I/O port pin
4
I JTAG pin (TDI)
3
O JTAG pin (TDO)
2
I/O General I/O port pin
PD1
CLKIN
3
1
I/O General I/O port pin
PD2
CSI
1
N/A I/O General I/O port pin
3.3V-V_CC
AV_CC
V_DD
3.3V or 5V
10
6
72
47
12
8
V_DD
3.3V or 5V
50
33
GND
13
9
GND
29
19
GND
69
45
NC
11 N/A
NC
17 N/A
Note: 1. N/A = Signal Not Available on 52-pin package.
V_CC - MCU Module
Analog V_CC Input
V_DD - PSD Module
V_DD - 3.3V for 3V
V_DD - 5V for 5V
V_DD - PSD Module
V_DD - 3.3V for 3V
V_DD - 5V for 5V
Function
Alternate 1
Alternate 2
All Port B pins
support:
1. PLD Macro-cell
outputs, or
2. PLD inputs, or
3. Latched
Address Out
(A0-A7)
SRAM Standby
voltage input
(V_STBY)
Optional JTAG
Status (TSTAT)
Optional JTAG
Status (TERR)
PLD Macrocell
output, or PLD input
PLD, Macrocell
output, or PLD input
PLD, Macrocell
output, or PLD input
PLD, Macrocell
output, or PLD input
1. PLD I/O
2. Clock input to
PLD and APD
1. PLD I/O
2. Chip select ot
PSD Module
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