UPSD33XX Datasheet, PDF (158/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Decode PLD (DPLD). The DPLD (Figure
64., page 159) generates the following memory
decode signals:
■ Eight Main Flash memory sector select signals
(FS0-FS7) with three product terms each
■ Four Secondary Flash memory sector select
signals (CSBOOT0-CSBOOT3) with three
product terms each
■ One SRAM select signal (RS0) with two
product terms
■ One select signal for the base address of 256
PSD Module device control and status
registers (CSIOP) with one product term
■ Two external chip-select output signals for
Port D pins, each with one product term (52-
pin devices only have one pin on Port D)
■ Two chip-select signals (PSEL0, PSEL1) used
to enable the 8032 data bus repeater function
(Peripheral I/O mode) for Port A on 80-pin
devices. Each has one product term.
A product term indicates the logical OR of two or
more inputs. For example, three product terms in
a DPLD output means the final output signal is ca-
pable of representing the logical OR of three differ-
ent input signals, each input signal representing
the logical AND of a combination of the 69 PLD in-
puts.
Using the signal FS0 for example, the user may
create a 3-product term chip select signal that is
logic true when any one of three different address
ranges are true... FS0 = address range 1 OR ad-
dress range 2 OR address range 3.
The phrase “one product term” is a bit misleading,
but commonly used in this context. One product
term is the logical AND of two or more inputs, with
no OR logic involved at all, such as the CSIOP sig-
nal in Figure 64., page 159.
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