UPSD33XX Datasheet, PDF (216/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Figure 92. Asynchronous RESET / Preset
tARPW
RESET/PRESET
INPUT
REGISTER
OUTPUT
tARP
AI02864
Figure 93. Asynchronous Clock Mode Timing (Product Term Clock)
tCHA
tCLA
CLOCK
tSA tHA
INPUT
REGISTERED
OUTPUT
tCOA
AI02859
Table 141. CPLD Macrocell Asynchronous Clock Mode Timing (5V PSD Module)
Symbol
Parameter
Conditions
Min
Max
PT Turbo Slew
Aloc Off Rate
Unit
Maximum Frequency
External Feedback
1/(t_SA+t_COA)
38.4
MHz
f_MAXA
Maximum Frequency
Internal Feedback (f_CNTA)
1/(t_SA+t_COA–10)
62.5
MHz
Maximum Frequency
Pipelined Data
1/(t_CHA+t_CLA)
71.4
MHz
t_SA Input Setup Time
7
+ 2 + 10
ns
t_HA Input Hold Time
8
ns
t_CHA Clock Input High Time
9
+ 10
ns
t_CLA Clock Input Low Time
9
+ 10
ns
t_COA Clock to Output Delay
21
+ 10 – 2 ns
t_ARDA CPLD Array Delay
Any macrocell
11
+2
ns
t_MINA Minimum Clock Period
1/f_CNTA
16
ns
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