UPSD33XX Datasheet, PDF (134/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
PSD Module Functional Description
Major functional blocks are shown in Figure
51., page 133. The next sections describe each
major block.
8032 Address/Data/Control Interface. These
signals attach directly to the MCU Module to im-
plement a typical multiplexed 8051-style bus be-
tween the two stacked die. The MCU instruction
prefetch and branch cache logic resides on the
MCU Module, leaving a standard 8051-style mem-
ory interface on the PSD Module.
The active-low reset signal originating from the
MCU Module goes to the PSD Module reset input
(RST). This reset signal can then be routed as an
external output from the uPSD33xx to the system
PC board, if needed, through any one of the PLD
output pins as active-high or active-low logic by
specifying logic equations in PSDsoft Express.
The 8032 address and data busses are routed
throughout the PSD Module as shown in Figure 51
connecting many elements on the PSD Module to
the 8032 MCU. The 8032 bus is not only connect-
ed to the memories, but also to the General PLD,
making it possible for the 8032 to directly read and
write individual logic macrocells inside the General
PLD.
Dual Flash Memories and IAP. uPSD33xx de-
vices contain two independent Flash memory ar-
rays. This means that the 8032 can read
instructions from one Flash memory array while
erasing or writing the other Flash memory array.
Concurrent operation like this enables robust re-
mote updates of firmware, also known as In-Appli-
cation Programming (IAP). IAP can occur using
any uPSD33xx interface (e.g., UART, I2C, SPI).
Concurrent memory operation also enables the
designer to emulate EEPROM memory within ei-
ther of the two Flash memory arrays for small data
sets that have frequent updates.
The 8032 can erase Flash memories by individual
sectors or it can erase an entire Flash memory ar-
ray at one time. Each sector in either Flash mem-
ory may be individually write protected, blocking
any WRITEs from the 8032 (good for boot and
start-up code protection). The Flash memories au-
tomatically go to standby between 8032 READ or
WRITE accesses to conserve power. Minimum
erase cycles is 100K and minimum data retention
is 15 years. Flash memory, as well as the entire
PSD Module may be programmed with the JTAG
In-System Programming (ISP) interface with no
8032 involvement, good for manufacturing and lab
development.
Main Flash Memory. The Main Flash memory is
divided into equal sized sectors that are individual-
ly selectable by the Decode PLD output signals,
named FSx, one signal for each Main Flash mem-
ory sector. Each Flash sector can be located at
any address within 8032 program address space
(accessed with PSEN) or data address space,
also known as 8032 XDATA space (accessed with
RD or WR), as defined with the software develop-
ment tool, PSDsoft Express. The user only has to
specify an address range for each segment and
specify if Main Flash memory will reside in 8032
data or program address space, and then PSEN,
RD, or WR are automatically activated for the
specified range. 8032 firmware is easily pro-
grammed into Main Flash memory using PSDsoft
Express or other software tools. See Table
75., page 135 for Main Flash sector sizes on the
various uPSD33xx devices.
Secondary Flash Memory. The smaller Second-
ary Flash memory is also divided into equal sized
sectors that are individually selectable by the De-
code PLD signals, named CSBOOTx, one signal
for each Secondary Flash memory sector. Each
sector can be located at any address within 8032
program address space (accessed with PSEN) or
XDATA space (accessed with RD or WR) as de-
fined with PSDsoft Express. The user only has to
specify an address range for each segment, and
specify if Secondary Flash memory will reside in
8032 data or program address space, and then
PSEN, RD, or WR are automatically activated for
the specified range. 8032 firmware is easily pro-
grammed into Secondary Flash memory using PS-
Dsoft Express and others. See Table
75., page 135 for Secondary Flash sector sizes.
SRAM. The SRAM is selected by a single signal,
named RS0, from the Decode PLD. SRAM may be
located at any address within 8032 XDATA space
(accessed with RD or WR), or optionally within
8032 program address space (accessed with
PSEN) to execute code from SRAM. The default
setting places SRAM in XDATA space only. These
choices are specified using PSDSoft Express,
where the user specifies an SRAM address range.
The user would also specify (at run-time) if SRAM
will additionally reside in 8032 program address
space, and then PSEN, RD, or WR are automati-
cally activated for the specified range. See Table
75., page 135 for SRAM sizes.
The SRAM may optionally be backed up by an ex-
ternal battery (or other DC source) to make its con-
tents non-volatile (see SRAM Standby Mode
(battery backup), page 193).
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