UPSD33XX Datasheet, PDF (63/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 35. BUSCON: Bus Control Register (SFR 9Dh, reset value EBh)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EPFQ
EBC
WRW[1:0]
RDW[1:0]
CW[1:0]
Details
Bit
Symbol
R/W
Definition
Enable Pre-Fetch Queue
7
EPFQ
R,W
0 = PFQ is disabled
1 = PFQ is enabled (default)
Enable Branch Cache
6
EBC
R,W
0 = BC is disabled
1 = BC is enabled (default)
WR Wait, number of MCU_CLK periods for WR write bus cycle during
any MOVX instruction
5:4
WRW[1:0]
R,W
00b: 4 clock periods
01b: 5 clock periods
10b: 6 clock periods (default)
11b: 7 clock periods
RD Wait, number of MCU_CLK periods for RD read bus cycle during any
MOVX instruction
3:2
RDW[1:0]
R,W
00b: 4 clock periods
01b: 5 clock periods
10b: 6 clock periods (default)
11b: 7 clock periods
Code Wait, number of MCU_CLK periods for PSEN read bus cycle
during any code byte fetch or during any MOVC code byte read
instruction. Periods will increase with PFQ stall
1:0
CW[1:0]
R,W
00b: 3 clock periods - exception, for MOVC instructions this setting
results 4 clock periods
01b: 4 clock periods
10b: 5 clock periods
11b: 6 clock periods (default)
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