UPSD33XX Datasheet, PDF (171/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 94. Port Configuration Setting Requirements
Port
Operating
Mode
Required Action in
PSDsoft Express to
Configure each Pin
Value that 8032
writes to csiop
Control Register at
run-time
Value that 8032
writes to csiop
Direction Register
at run-time
Value that 8032
writes to Bit 7
(PIO_EN) of csiop VM
Register at run-time
MCU I/O
Choose the MCU I/O
function and declare the
pin name
Logic '0' (default)
Logic 1 = Out of
uPSD
N/A
Logic 0 = Into uPSD
PLD I/O
Choose the PLD function
type, declare pin name,
and specify logic
N/A
equation(s)
Direction register
has no effect on a
pin if pin is driven
N/A
from OMC output
Latched Address
Output
Choose Latched Address
Out function, declare pin Logic '1'
name
Logic '1' Only
N/A
Choose Peripheral I/O
Peripheral I/O
mode function and
specify address range in
N/A
N/A
PIO_EN Bit = Logic 1
(default is '0')
DPLD for PSELx
No action required in
PSDsoft to get 4-pin
4-PIN JTAG ISP
JTAG. By default TDO,
TDI, TCK, TMS are
N/A
N/A
N/A
dedicated JTAG
functions.
6-PIN JTAG ISP
(faster
programming)
Choose JTAG TSTAT
function for pin PC3 and
JTAG TERR function for
pin PC4.
N/A
N/A
N/A
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