UPSD33XX Datasheet, PDF (113/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
SPI Bus Features and Communication Flow
The SPICLK signal is a gated clock generated
from the uPSD33xx (Master) and regulates the
flow of data bits. The Master may transmit at a va-
riety of baud rates, and the SPICLK signal will
clock one period for each bit of transmitted data.
Data is shifted on one edge of SPICLK and sam-
pled on the opposite edge.
The SPITxD signal is generated by the Master and
received by the Slave device. The SPIRxD signal
is generated by the Slave device and received by
the Master. There may be no more than one Slave
device transmitting data on SPIRxD at any given
time in a multi-Slave configuration. Slave selection
is accomplished when a Slave’s “Slave Select”
(SS) input is permanently grounded or asserted
active-low by a Master device. Slave devices that
are not selected do not interfere with SPI activities.
Slave devices ignore SPICLK and keep their
MISO output pins in high-impedance state when
not selected.
The SPI specification allows a selection of clock
polarity and clock phase with respect to data. The
uPSD33xx supports the choice of clock polarity,
but it does not support the choice of clock phase
(phase is fixed at what is typically known as
CPHA = 1). See Figure 43. and Figure
44., page 114 for SPI data and clock relationships.
Referring to these figures (43 and 44), when the
phase mode is defined as such (fixed at
CPHA =1), in a new SPI data frame, the Master
device begins driving the first data bit on SPITxD
at the very first edge of the first clock period of SPI-
CLK.
The Slave device will use this first clock edge as a
transmission start indicator, and therefore the
Slave’s Slave Select input signal may remain
grounded in a single-Master/single-Slave configu-
ration (which means the user does not have to use
the SPISEL signal from uPSD33xx in this case).
The SPI specification does not specify high-level
protocol for data exchange, only low-level bit-seri-
al transfers are defined.
Full-Duplex Operation
When an SPI transfer occurs, 8 bits of data are
shifted out on one pin while a different 8 bits of
data are simultaneously shifted in on a second pin.
Another way to view this transfer is that an 8-bit
shift register in the Master and another 8-bit shift
register in the Slave are connected as a circular
16-bit shift register. When a transfer occurs, this
distributed shift register is shifted 8 bit positions;
thus, the data in the Master and Slave devices are
effectively exchanged (see Figure 42.).
Bus-Level Activity
Figure 43. details an SPI receive operation (with
respect to bus Master) and Figure 44. details an
SPI transmit operation. Also shown are internal
flags available to firmware to manage data flow.
These flags are accessed through a number of
SFRs.
Note: The uPSD33xx SPI interface SFRs allow
the choice of transmitting the most significant bit
(MSB) of a byte first, or the least significant bit
(LSB) first. The same bit-order applies to data re-
ception. Figures 43 and 44 illustrate shifting the
LSB first.
Figure 42. SPI Full-Duplex Data Exchange
Master Device
8-Bit Shift
Register
SPIRxD
SPITxD
SPI Bus
Slave Device
MISO
MOSI
8-Bit Shift
Register
SPICLK
SCLK
Baud Rate
Generator
SS
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