UPSD33XX Datasheet, PDF (40/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
INTERRUPT SYSTEM
The uPSD33xx has an 11-source, two priority level
interrupt structure summarized in Table 16.
Firmware may assign each interrupt source either
high or low priority by writing to bits in the SFRs
named, IP and IPA, shown in Table 16. An inter-
rupt will be serviced as long as an interrupt of
equal or higher priority is not already being ser-
viced. If an interrupt of equal or higher priority is
being serviced, the new interrupt will wait until it is
finished before being serviced. If a lower priority
interrupt is being serviced, it will be stopped and
the new interrupt is serviced. When the new inter-
rupt is finished, the lower priority interrupt that was
stopped will be completed. If new interrupt re-
quests are of the same priority level and are re-
ceived simultaneously, an internal polling
sequence determines which request is selected
for service. Thus, within each of the two priority
levels, there is a second priority structure deter-
mined by the polling sequence.
Firmware may individually enable or disable inter-
rupt sources by writing to bits in the SFRs named,
IE and IEA, shown in Table 16., page 41. The SFR
named IE contains a global disable bit (EA), which
can be cleared to disable all 11 interrupts at once,
as shown in Table 17., page 43. Figure
13., page 42 illustrates the interrupt priority, poll-
ing, and enabling process.
Each interrupt source has at least one interrupt
flag that indicates whether or not an interrupt is
pending. These flags reside in bits of various
SFRs shown in Table 16., page 41.
All of the interrupt flags are latched into the inter-
rupt control system at the beginning of each MCU
machine cycle, and they are polled at the begin-
ning of the following machine cycle. If polling de-
termines one of the flags was set, the interrupt
control system automatically generates an LCALL
to the user’s Interrupt Service Routine (ISR) firm-
ware stored in program memory at the appropriate
vector address.
The specific vector address for each of the inter-
rupt sources are listed in Table 16., page 41. How-
ever, this LCALL jump may be blocked by any of
the following conditions:
– An interrupt of equal or higher priority is
already in progress
– The current machine cycle is not the final cycle
in the execution of the instruction in progress
– The current instruction involves a write to any
of the SFRs: IE, IEA, IP, or IPA
– The current instruction is an RETI
Note: Interrupt flags are polled based on a sample
taken in the previous MCU machine cycle. If an in-
terrupt flag is active in one cycle but is denied ser-
viced due to the conditions above, and then later it
is not active when the conditions above are finally
satisfied, the previously denied interrupt will not be
serviced. This means that active interrupts are not
remembered. Every poling cycle is new.
Assuming all of the listed conditions are satisfied,
the MCU executes the hardware generated
LCALL to the appropriate ISR. This LCALL pushes
the contents of the PC onto the stack (but it does
not save the PSW) and loads the PC with the ap-
propriate interrupt vector address. Program exe-
cution then jumps to the ISR at the vector address.
Execution precedes in the ISR. It may be neces-
sary for the ISR firmware to clear the pending in-
terrupt flag for some interrupt sources, because
not all interrupt flags are automatically cleared by
hardware when the ISR is called, as shown in Ta-
ble 16., page 41. If an interrupt flag is not cleared
after servicing the interrupt, an unwanted interrupt
will occur upon exiting the ISR.
After the interrupt is serviced, the last instruction
executed by the ISR is RETI. The RETI informs
the MCU that the ISR is no longer in progress and
the MCU pops the top two bytes from the stack
and loads them into the PC. Execution of the inter-
rupted program continues where it left off.
Note: An ISR must end with a RETI instruction,
not a RET. An RET will not inform the interrupt
control system that the ISR is complete, leaving
the MCU to think the ISR is still in progress, mak-
ing future interrupts impossible.
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