UPSD33XX Datasheet, PDF (172/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
MCU I/O Mode. In MCU I/O mode, the 8032 on
the MCU Module expands its own I/O by using the
I/O Ports on the PSD Module. The 8032 can read
PSD Module I/O pins, set the direction of the I/O
pins, and change the output state of I/O pins by ac-
cessing the Data In, Direction, and Data Out csiop
registers respectively at run-time.
To implement MCU I/O mode, each desired pin is
specified in PSDsoft Express as MCU I/O function
and given a pin name. Then 8032 firmware is writ-
ten to set the Direction bit for each corresponding
pin during initialization routines (0 = In, 1 = Out of
the chip), then the 8032 firmware simply reads the
corresponding Data In register to determine the
state of an I/O pin, or writes to a Data Out register
to set the state of a pin. The Direction of each pin
may be changed dynamically by the 8032 if de-
sired. A mixture of input and output pins within a
single port is allowed. Figure 69., page 169 shows
the Data In, Data Out, and Direction signal paths.
The Data In registers are defined in Table 95 to
Table 98. The Data Out registers are defined in
Table 99 to Table 102., page 173. The Direction
registers are defined in Table 103 to Table
106., page 173.
Table 95. MCU I/O Mode Port A Data In Register⁽¹⁾ (address = csiop + offset 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PA7
PA6
PA5
PA4
PA3
PA2
PA1
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’
Bit 0
PA0
Table 96. MCU I/O Mode Port B Data In Register (address = csiop + offset 01h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PB7
PB6
PB5
PB4
PB3
Note: For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’
PB2
PB1
Bit 0
PB0
Table 97. MCU I/O Mode Port C Data In Register (address = csiop + offset 10h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PC7
X
X
PC4
PC3
PC2
X
Note: 1. X = Not guaranteed value, can be read either '1' or '0.'
2. For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’
Table 98. MCU I/O Mode Port D Data In Register (address = csiop + offset 11h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
X
X
X
X
X
PD2⁽³⁾
PD1
Note: 1. X = Not guaranteed value, can be read either '1' or '0.'
2. For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’
3. Not available on 52-pin uPSD33xx devices
Table 99. MCU I/O Mode Port A Data Out Register⁽¹⁾ (address = csiop + offset 04h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PA7
PA6
PA5
PA4
PA3
PA2
PA1
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’
3. Default state of register is 00h after reset or power-up
Table 100. MCU I/O Mode Port B Data Out Register (address = csiop + offset 05h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
Note: 1. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’
2. Default state of register is 00h after reset or power-up
Bit 0
X
Bit 0
X
Bit 0
PA0
Bit 0
PB0
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