UPSD33XX Datasheet, PDF (185/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Port D Structure. Port D has two I/O pins (PD1,
PD2) on 80-pin uPSD33xx devices, and just one
pin (PD1) on 52-pin devices, supporting the follow-
ing operating modes:
■ MCU I/O Mode
■ DPLD Output Mode for External Chip Selects,
ECS1, ECS2. This does not consume OMCs
in the GPLD.
■ PLD Input Mode – direct input to the PLD Input
Bus available to DPLD and GPLD. Does not
use IMCs
See Figure 77., page 186 for detail.
Port D pins can also be configured in PSDsoft as
pins for other dedicated functions:
– PD1 can be used as a common clock input to
all 16 OMC Flip-flops (see OMCs, page 136)
and also the Automatic Power-Down
(APD), page 189.
– PD2 can be used as a common chip select
signal (CSI) for the Flash and SRAM
memories on the PSD Module (see Chip Se-
lect Input (CSI), page 191). If driven to logic ’1’
by an external source, CSI will force all
memories into standby mode regardless of
what other internal memory select signals are
doing on the PSD Module. This is specified in
PSDsoft as “PSD Chip Select Input, CSI”.
Port D also supports the Fast Slew Rate output
drive type option using the csiop Drive Select reg-
isters.
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