UPSD33XX Datasheet, PDF (34/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 8. Data Transfer Instruction Set
Mnemonic⁽¹⁾
and Use
Description
MOV
A, Rn
Move register to ACC
MOV
A, direct
Move direct byte to ACC
MOV
A, @Ri
Move indirect SRAM to ACC
MOV
A, #data
Move immediate data to ACC
MOV
Rn, A
Move ACC to register
MOV
Rn, direct
Move direct byte to register
MOV
Rn, #data
Move immediate data to register
MOV
direct, A
Move ACC to direct byte
MOV
direct, Rn
Move register to direct byte
MOV
direct, direct
Move direct byte to direct
MOV
direct, @Ri
Move indirect SRAM to direct byte
MOV
direct, #data
Move immediate data to direct byte
MOV
@Ri, A
Move ACC to indirect SRAM
MOV
@Ri, direct
Move direct byte to indirect SRAM
MOV
@Ri, #data
Move immediate data to indirect SRAM
MOV
DPTR, #data16
Load Data Pointer with 16-bit constant
MOVC
A, @A+DPTR
Move code byte relative to DPTR to ACC
MOVC
A, @A+PC
Move code byte relative to PC to ACC
MOVX
A, @Ri
Move XDATA (8-bit addr) to ACC
MOVX
A, @DPTR
Move XDATA (16-bit addr) to ACC
MOVX
@Ri, A
Move ACC to XDATA (8-bit addr)
MOVX
@DPTR, A
Move ACC to XDATA (16-bit addr)
PUSH
direct
Push direct byte onto stack
POP
direct
Pop direct byte from stack
XCH
A, Rn
Exchange register with ACC
XCH
A, direct
Exchange direct byte with ACC
XCH
A, @Ri
Exchange indirect SRAM with ACC
XCHD
A, @Ri
Exchange low-order digit indirect SRAM with ACC
Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.
Length/Cycles
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
2 byte/2 cycle
2 byte/1 cycle
2 byte/1 cycle
2 byte/2 cycle
3 byte/2 cycle
2 byte/2 cycle
3 byte/2 cycle
1 byte/1 cycle
2 byte/2 cycle
2 byte/1 cycle
3 byte/2 cycle
1 byte/2 cycle
1 byte/2 cycle
1 byte/2 cycle
1 byte/2 cycle
1 byte/2 cycle
1 byte/2 cycle
2 byte/2 cycle
2 byte/2 cycle
1 byte/1 cycle
2 byte/1 cycle
1 byte/1 cycle
1 byte/1 cycle
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