UPSD33XX Datasheet, PDF (165/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Loading and Reading OMCs. Each of the two
OMC groups (eight OMCs each) occupies a byte
in csiop space, named MCELLAB and MCELLBC
(see Table 86 and Table 87). When the 8032
writes or reads these two OMC registers in csiop it
is accessing each of the OMCs through it’s 8-bit
data bus, with the bit assignment shown in Table
85., page 164. Sometimes it is important to know
the bit assignment when the user builds GPLD log-
ic that is accessed by the 8032. For example, the
user may create a 4-bit counter that must be load-
ed and read by the 8032, so the user must know
which nibble in the corresponding csiop OMC reg-
ister the firmware must access. The fitter report
generated by PSDsoft Express will indicate how it
assigned the OMCs and data bus bits to the logic.
The user can optionally force PSDsoft Express to
assign logic to specific OMCs and data bus bits if
desired by using the ‘PROPERTY’ statement in
PSDsoft Express. Please see the PSDsoft Ex-
press User’s Manual for more information on OMC
assignments.
Loading the OMC flip-flops with data from the
8032 takes priority over the PLD logic functions.
As such, the preset, clear, and clock inputs to the
flip-flop can be asynchronously overridden when
the 8032 writes to the csiop registers to load the in-
dividual OMCs.
Table 86. Output Macrocell MCELLAB (address = csiop + offset 20h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCELLAB7 MCELLAB6 MCELLAB5 MCELLAB4 MCELLAB3 MCELLAB2 MCELLAB1 MCELLAB0
Note: All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on reset)
Table 87. Output Macrocell MCELLBC (address = csiop + offset 21h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MCELLBC7 MCELLBC6 MCELLBC5 MCELLBC4 MCELLBC3 MCELLBC2 MCELLBC1 MCELLBC0
Note: All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on reset)
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