UPSD33XX Datasheet, PDF (75/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 41. T2CON: Timer 2 Control Register (SFR C8h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Details
Bit
Symbol
R/W
Definition
Timer 2 flag, causes interrupt if enabled.
7
TF2
R,W
TF2 is set by hardware upon overflow. Must be cleared by firmware. TF2
will not be set when either RCLK or TCLK =1.
Timer 2 flag, causes interrupt if enabled.
6
EXF2
R,W
EXF2 is set when a capture or reload is caused by a negative transition
on T2X pin and EXEN2 = 1. EXF2 must be cleared by firmware.
UART0 Receive Clock control.
5
RCLK⁽¹⁾
R,W
When RCLK = 1, UART0 uses Timer 2 overflow pulses for its receive
clock in Modes 1 and 3. RCLK=0, Timer 1 overflow is used for its receive
clock
UART0 Transmit Clock control.
4
TCLK⁽¹⁾
R,W
When TCLK = 1, UART0 uses Timer 2 overflow pulses for its transmit
clock in Modes 1 and 3. TCLK=0, Timer 1 overflow is used for transmit
clock
Timer 2 External Enable.
3
EXEN2
R,W
When EXEN2 = 1, capture or reload results when negative edge on pin
T2X occurs. EXEN2 = 0 causes Timer 2 to ignore events at pin T2X.
Timer 2 run control.
2
TR2
R,W
1 = Timer/Counter 2 is on, 0 = Timer Counter 2 is off.
Counter or Timer function select.
1
C/T2
R,W
When C/T2 = 0, function is timer, clocked by internal clock. When C/T2 =
1, function is counter, clocked by signal sampled on external pin, T2.
Capture/Reload.
When CP/RL2 = 1, capture occurs on negative transition at pin T2X if
0
CP/RL2
R,W
EXEN2 = 1. When CP/RL2 = 0, auto-reload occurs when Timer 2
overflows, or on negative transition at pin T2X when EXEN2=1. When
RCLK = 1 or TCLK = 1, CP/RL2 is ignored, and Timer 2 is forced to auto-
reload upon Timer 2 overflow
Note: 1. The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact same function as RCLK and TCLK.
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