UPSD33XX Datasheet, PDF (115/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
SPI SFR Registers
Six SFR registers control the SPI interface:
■ SPICON0 (Table 59., page 117) for interface
control
■ SPICON1 (Table 60., page 118) for interrupt
control
■ SPITDR (SFR D4h, Write only) holds byte to
transmit
■ SPIRDR (SFR D5h, Read only) holds byte
received
■ SPICLKD (Table 61., page 118) for clock
divider
■ SPISTAT (Table 62., page 119) holds
interface status
Figure 45. SPI Interface, Master Mode Only
The SPI interface functional block diagram (Figure
45.) shows these six SFRs. Both the transmit and
receive data paths are double-buffered, meaning
that continuous transmitting or receiving (back-to-
back transfer) is possible by reading from SPIRDR
or writing data to SPITDR while shifting is taking
place. There are a number of flags in the SPISTAT
register that indicate when it is full or empty to as-
sist the 8032 MCU in data flow management.
When enabled, these status flags will cause an in-
terrupt to the MCU.
INTR
to
8032
8032 MCU DATA BUS
8
8
SPICON0, SPICON1
- CONTROL REGISTERS
SPITDR - TRANSMIT REGISTER
8
8-bit SHIFT REGISTER
TIMING AND CONTROL
8
SPIRxD /
P1.5 or P4.5
SPISTAT - STATUS REGISTER
8
SPIRDR - RECEIVE REGISTER
8
SPITxD / P1.6 or P4.6
PERIPH_CLK
(fOSC)
CLOCK
DIVIDE
÷1
÷4
÷8
÷16
÷32
÷64
÷128
CLOCK
GENERATE
SPISEL / P1.7 or P4.7
SPICLK / P1.4 or P4.4
8
SPICLKD - DIVIDE SELECT
AI10486
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