UPSD33XX Datasheet, PDF (210/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Figure 88. External PSEN/READ Cycle (80-pin Device Only)
tLHLL
tLLPL
ALE
PSEN
RD
MCU
AD0 - AD7
MCU
A8 - A11
tAVLL
tPLPH
tLLAX
A0-A7
tAZPL
tAVIV
INSTR
IN
A8-A11
tPXAV
tPXIZ
tPXIX
A0-A7
A8-A11
AI07875
Table 132. External PSEN or READ Cycle AC Characteristics (3V or 5V Device)
Symbol
Parameter
40MHz Oscillator⁽¹⁾
Min
Max
Variable Oscillator
1/t_CLCL = 8 to 40MHz
Min
Max
t_LHLL ALE pulse width
17
t_CLCL – 8
t_AVLL Address setup to ALE
13
t_CLCL – 12
t_LLAX Address hold after ALE
7.5
0.5t_CLCL – 5
t_LLPL ALE to PSEN or RD
7.5
0.5t_CLCL – 5
t_{PLPH PSEN or RD pulse width}⁽²⁾
40
nt_CLCL – 10
t_PXIX
Input instruction/data hold after
PSEN or RD
2
2
t_PHIZ
Input instruction/data float after
PSEN or RD
10.5
0.5t_CLCL – 2
t_PXAV Address hold after PSEN or RD
7.5
0.5t_CLCL – 5
t_{AVIV Address to valid instruction/data in}⁽²⁾
70
mt_CLCL – 5
t_AZPL Address float to PSEN or RD
–2
–2
Note: 1. BUSCON Register is configured for 4 PFQCLK.
2. Refer to Table 133 for “n” and “m” values.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 133. n, m, and x, y Values
# of PFQCLK in
BUSCON Reg.
PSEN (code) Cycle
n
m
3
1
2
4
2
3
5
3
4
6
4
5
7
-
-
READ Cycle
n
m
-
-
2
3
3
4
4
5
5
6
WRITE Cycle
x
y
-
-
2
1
3
2
4
3
5
4
210/231