UPSD33XX Datasheet, PDF (195/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
JTAG ISP and JTAG Debug. An IEEE 1149.1
serial JTAG interface is used on uPSD33xx devic-
es for ISP (In-System Programming) of the PSD
module, and also for debugging firmware on the
MCU Module. IEEE 1149.1 Boundary Scan oper-
ations are not supported in the uPSD33xx.
The main advantage of JTAG ISP is that a blank
uPSD33xx device may be soldered to a circuit
board and programmed with no involvement of the
8032, meaning that no 8032 firmware needs to be
present for ISP. This is good for manufacturing, for
field updates, and for easy code development in
the lab. JTAG-based programmers and debug-
gers for uPSD33xx are available from STMicro-
electronics and 3rd party vendors.
ISP is different than IAP (In-Application Program-
ming). IAP involves the 8032 to program Flash
memory over any interface supported by the 8032
(e.g., UART, SPI, I2C), which is good for remote
updates over a communication channel.
uPSD33xx devices support both ISP and IAP. The
entire PSD Module (Flash memory and PLD) may
be programmed with JTAG ISP, but only the Flash
memories may be programmed using IAP.
JTAG Chaining Inside the Package. JTAG pro-
tocol allows serial “chaining” of more than one de-
vice in a JTAG chain. The uPSD33xx is
assembled with a stacked die process combining
the PSD Module (one die) and the MCU Module
(the other die). These two die are chained together
within the uPSD33xx package. The standard
JTAG interface has four basic signals:
■ TDI - Serial data into device
■ TDO - Serial data out of device
■ TCK - Common clock
■ TMS - Mode Selection
Every device that supports IEEE 1149.1 JTAG
communication contains a Test Access Port (TAP)
controller, which is a small state machine to man-
age JTAG protocol and serial streams of com-
mands and data. Both the PSD Module and the
MCU Module each contain a TAP controller.
Figure 80 illustrates how these die are chained
within a package. JTAG programming/test equip-
ment will connect externally to the four IEEE
1149.1 JTAG pins on Port C. The TDI pin on the
uPSD33xx package goes directly to the PSD Mod-
ule first, then exits the PSD Module through TDO.
TDO of the PSD Module is connected to TDI of the
MCU Module. The serial path is completed when
TDO of the MCU Module exits the uPSD33xx
package through the TDO pin on Port C. The
JTAG signals TCK and TMS are common to both
modules as specified in IEEE 1149.1. When JTAG
devices are chained, typically one devices is in
BYPASS mode while another device is executing
a JTAG operation. For the uPSD33xx, the PSD
Module is in BYPASS mode while debugging the
MCU Module, and the MCU Module is in BYPASS
mode while performing ISP on the PSD Module.
The RESET_IN input pin on the uPSD33xx pack-
age goes to the MCU Module, and this module will
generate the RST reset signal for the PSD Mod-
ule. These reset signals are totally independent of
the JTAG TAP controllers, meaning that the JTAG
channel is operational when the modules are held
in reset. It is required to assert RESET_IN during
ISP. STMicroelectronics and 3rd party JTAG ISP
tools will automatically assert a reset signal during
ISP. However, this reset signal must be connected
to RESET_IN as shown in examples in Figure Fig-
ure 81., page 196 and Figure 82., page 198.
Figure 80. JTAG Chain in uPSD33xx Package
OPTIONAL
DEBUG
RESET_IN
MCU MODULE
uPSD33XX
8032 MCU
RESET
JTAG TAP
CONTROLLER
TDO TMS TCK TDI
JTAG TDO
JTAG TCK
IEEE 1149.1
JTAG TMS
JTAG TDI
PC3 / TSTAT
OPTIONAL
PC4 / TERR
TDI
TSTAT
TERR
TMS TCK TDO
JTAG TAP
CONTROLLER
RST
MAIN
2ND
FLASH FLASH PLD
MEMORY MEMORY
PSD MODULE
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