UPSD33XX Datasheet, PDF (22/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
General Purpose Registers (R0 - R7)
There are four banks of eight general purpose 8-
bit registers (R0 - R7), but only one bank of eight
registers is active at any given time depending on
the setting in the PSW word (described next). R0 -
R7 are generally used to assist in manipulating
values and moving data from one memory location
to another. These register banks physically reside
in the first 32 locations of 8032 internal DATA
SRAM, starting at address 00h. At reset, only the
first bank of eight registers is active (addresses
00h to 07h), and the stack begins at address 08h.
Program Status Word (PSW)
The PSW is an 8-bit register which stores several
important bits, or flags, that are set and cleared by
many 8032 instructions, reflecting the current
state of the MCU core. Figure 12., page 22 shows
the individual flags.
Carry Flag (CY). This flag is set when the last
arithmetic operation that was executed results in a
carry (addition) or borrow (subtraction). It is
cleared by all other arithmetic operations. The CY
flag is also affected by Shift and Rotate Instruc-
tions.
Auxiliary Carry Flag (AC). This flag is set when
the last arithmetic operation that was executed re-
sults in a carry into (addition) or borrow from (sub-
traction) the high-order nibble. It is cleared by all
other arithmetic operations.
General Purpose Flag (F0). This is a bit-addres-
sable, general-purpose flag for use under software
control.
Register Bank Select Flags (RS1, RS0). These
bits select which bank of eight registers is used
during R0 - R7 register accesses (see Table 4)
Overflow Flag (OV). The OV flag is set when: an
ADD, ADDC, or SUBB instruction causes a sign
change; a MUL instruction results in an overflow
(result greater than 255); a DIV instruction causes
a divide-by-zero condition. The OV flag is cleared
by the ADD, ADDC, SUBB, MUL, and DIV instruc-
tions in all other cases. The CLRV instruction will
clear the OV flag at any time.
Parity Flag (P). The P flag is set if the sum of the
eight bits in the Accumulator is odd, and P is
cleared if the sum is even.
Table 4. .Register Bank Select Addresses
RS1
RS0
Register
Bank
8032 Internal
DATA Address
0
0
0
00h - 07h
0
1
1
08h - 0Fh
1
0
2
10h - 17h
1
1
3
18h - 1Fh
Figure 12. Program Status Word (PSW) Register
MSB
PSW ^{CY AC FO RS1 RS0 OV}
Carry Flag
Auxillary Carry Flag
General Purpose Flag
LSB
P _{Reset Value 00h}
Parity Flag
Bit not assigned
Overflow Flag
Register Bank Select Flags
(to select Bank0-3)
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