UPSD33XX Datasheet, PDF (117/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Table 59. SPICON0: Control Register 0 (SFR D6h, Reset Value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
–
TE
RE
SPIEN
SSEL
FLSB
SBO
–
Details
Bit
Symbol
R/W
Definition
7
–
–
Reserved
Transmitter Enable
6
TE
RW
0 = Transmitter is disabled
1 = Transmitter is enabled
Receiver Enable
5
RE
RW
0 = Receiver is disabled
1 = Receiver is enabled
SPI Enable
4
SPIEN
RW
0 = Entire SPI Interface is disabled
1 = Entire SPI Interface is enabled
Slave Selection
3
SSEL
RW
0 = SPISEL output pin is constant logic '1' (slave device not selected)
1 = SPISEL output pin is logic '0' (slave device is selected) during data
transfers
First LSB
2
FLSB
RW
0 = Transfer the most significant bit (MSB) first
1 = Transfer the least significant bit (LSB) first
Sampling Polarity
1
SPO
–
0 = Sample transfer data at the falling edge of clock (SPICLK is '0' when
idle)
1 = Sample transfer data at the rising edge of clock (SPICLK is '1' when
idle)
0
–
–
Reserved
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