UPSD33XX Datasheet, PDF (156/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
PLDs. The PSD Module contains two PLDs: the
Decode PLD (DPLD), and the General PLD
(GPLD), as shown in Figure 63., page 157. Both
PLDs are fed by a common PLD input signal bus,
and additionally, the GPLD is connected to the
8032 data bus.
PLD logic is specified using PSDsoft Express and
programmed into the PSD Module using the JTAG
ISP channel. PLD logic is non-volatile and avail-
able at power-up. PLDs may not be programmed
by the 8032. The PLDs have selectable levels of
performance and power consumption.
The DPLD performs address decoding, and gen-
erates select signals for internal and external com-
ponents, such as memory, registers, and I/O ports.
The DPLD can generate External Chip-Select
(ECS1-ECS2) signals on Port D.
The GPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, encoding and decoding logic. These logic
functions can be constructed from a combination
of 16 Output Macrocells (OMC), 20 Input Macro-
cells (IMC), and the AND-OR Array.
Routing of the 16 OMCs outputs can be divided
between pins on three Ports A, B, or C by the OMC
Allocator as shown in Figure 67., page 163. Eight
of the 16 OMCs that can be routed to pins on Port
A or Port B and are named MCELLAB0-
MCELLAB7. The other eight OMCs to be routed to
pins on Port B or Port C and are named
MCELLBC0-MCELLBC7. This routing depends on
the pin number assignments that are specified in
PSDsoft Express for “PLD Outputs” in the Pin Def-
inition section. OMC outputs can also be routed in-
ternally (not to pins) used as buried nodes to
create shifters, counters, etc.
The AND-OR Array is used to form product terms.
These product terms are configured from the logic
definitions entered in PSDsoft Express. A PLD In-
put Bus consisting of 69 signals is connected to
both PLDs. Input signals are shown in Table 84,
both the true and compliment versions of each of
these signals are available at inputs to each PLD.
Note: The 8032 data bus, D0 - D7, does not route
directly to PLD inputs. Instead, the 8032 data bus
has indirect access to the GPLD (not the DPLD)
when the 8032 reads and writes the OMC and IMC
registers within csiop address space.
Turbo Bit and PLDs. The PLDs can minimize
power consumption by going to standby after ALL
the PLD inputs remain unchanged for an extended
time (about 70ns). When the Turbo Bit is set to log-
ic one (Bit 3 of the csiop PMMR0 Register), Turbo
mode is turned off and then this automatic standby
mode is achieved. Turning off Turbo mode in-
creases propagation delays while reducing power
consumption. The default state of the Turbo Bit is
logic zero, meaning Turbo mode is on. Additional-
ly, four bits are available in the csiop PMMR0 and
PMMR2 Registers to block the 8032 bus control
signals (RD, WR, PSEN, ALE) from entering the
PLDs. This reduces power consumption and can
be used only when these 8032 control signals are
not used in PLD logic equations. See Power
Management, page 187.
Table 84. DPLD and GPLD Inputs
Input Source
Input Name
Number
of
Signals
8032 Address Bus
A0-A15
16
8032 Bus Control Signals
PSEN, RD, WR,
ALE
4
Reset from MCU Module RESET
1
Power-Down from Auto-
Power Down Counter
PDN
1
PortA Input Macrocells
(80-pin devices only)
PA0-PA7
8
PortB Input Macrocells PB0-PB7
8
PortC Input Macrocells
PC2, PC3, PC4,
PC7
4
Port D Inputs
(52-pin devices have only PD1, PD2
2
PD1)
Page Register
PGR0-PGR7
8
Macrocell OMC bank AB MCELLAB
Feedback
FB0-7
8
Macrocell OMC bank BC MCELLBC
Feedback
FB0-7
8
Flash memory Status Bit Ready/Busy
1
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