UPSD33XX Datasheet, PDF (193/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
PLD Blocking Bits. Blocking specific signals
from entering the PLDs using bits of the csiop
PMMR registers can further reduce PLD AC cur-
rent consumption by lowering the effective com-
posite frequency of inputs to the PLDs.
Blocking 8032 Bus Control Signals. When the
8032 is active on the MCU Module, four bus con-
trol signals (RD, WR, PSEN, and ALE) are con-
stantly transitioning to manage 8032 bus traffic.
Each time one of these signals has a transition
from logic ’1’ to '0,' or 0 to '1,' it will wake up the
PLDs if operating in non-Turbo mode, or when in
Turbo mode it will cause the affected PLD gates to
draw current. If equations in the DPLD or GPLD do
not use the signals RD, WR, PSEN, or ALE then
these signals can be blocked which will reduce the
AC current component substantially. These bus
control signals are rarely used in DPLD equations
because they are routed in silicon directly to the
memory arrays of the PSD Module, bypassing the
PLDs. For example, it is NOT necessary to qualify
a memory chip select signal with an MCU write
strobe, such as “fs0 = address range & !WR_”.
Only “fs0 = address range” is needed.
Each of the 8032 bus control signals may be
blocked individually by writing to Bits 2, 3, 4, and 5
of the PMMR2 register shown in Table
118., page 188. Blocking any of these four bus
control signals only prevents them from reaching
the PLDs, but they will always go to the memories
directly.
However, sometimes it is necessary to use these
8032 bus control signals in the GPLD when creat-
ing interface signals to external I/O peripherals.
But it is still possible to save power by dynamically
unblocking the bus signals before reading/writing
the external device, then blocking the signals after
the communication is complete.
The user can also block an input signal coming
from pin PC7 to the PLD input bus if desired by
writing to Bit 6 of PMMR2.
Blocking Common Clock, CLKIN. The input
CLKIN (from pin PD1) can be blocked to reduce
current consumption. CLKIN is used as a common
clock input to all OMC flip-flips, it is a general input
to the PLD input bus, and it is used to clock the
APD counter. In PSDsoft Express, the function of
pin PD1 must be specified as “Common Clock In-
put, CLKIN” before programming the device with
JTAG to get the CLKIN function.
Bit 4 of PMMR0 can be set to logic ’1’ to block
CLKIN from reaching the PLD input bus, but
CLKIN will still reach the APD counter.
Bit 5 of PMMR0 can be set to logic ’1’ to block
CLKIN from reaching the OMC flip-flops only, but
CLKIN is still available to the PLD input bus and
the APD counter.
See Table 117., page 188 for details.
SRAM Standby Mode (battery backup). The
SRAM on the PSD Module may optionally be
backed up by an external battery (or other DC
source) to make its contents non-volatile. This is
achieved by connecting a battery to pin PC2 on
Port C and selecting the “SRAM Standby” function
for pin PC2 within PSDsoft Express. Automatic
voltage supply cross-over circuitry is built into the
PSD Module to switch SRAM supply to battery as
soon as V_DD drops below the voltage level of the
battery. SRAM contents are protected while bat-
tery voltage is greater than 2.0V. Pin PC4 on Port
C can be used as an output to indicate that a bat-
tery switch-over has occurred. This is configured
in PSDsoft Express by selecting the “Standby On
Indicator” option for pin PC4.
PSD Module Reset Conditions
The PSD Module receives a reset signal from the
MCU Module. This reset signal is referred to as the
“RST” input in PSD Module documentation, and it
is active-low when asserted. The character of the
RST signal generated from the MCU Module is de-
scribed
in
SUPERVISORY
FUNCTIONS, page 65.
Upon power-up, and while RST is asserted, the
PSD Module immediately loads its configuration
from non-volatile bits to configure the PLDs and
other items. PLD logic is operational and ready for
use well before RST is de-asserted. The state of
PLD outputs are determined by equations speci-
fied in PSDsoft Express.
The Flash memories are reset to Read Array
mode after any assertion of RST (even if a pro-
gram or erase operation is occurring).
Flash memory WRITE operations are automatical-
ly prevented while V_DD is ramping up until it rises
above the V_LKO voltage threshold at which time
Flash memory WRITE operations are allowed.
Once the uPSD33xx is up and running, any subse-
quent reset operation is referred to as a warm re-
set, until power is turned off again. Some PSD
Module functions are reset in different ways de-
pending if the reset condition was caused from a
power-up reset or a warm reset. Table
121., page 194 summarizes how PSD Module
functions are affected by power-up and warm re-
sets, as well as the affect of PSD Module power-
down mode (from APD).
The I/O pins of PSD Module Ports A, B, C, and D
do not have weak internal pull-ups.
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