UPSD33XX Datasheet, PDF (112/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
SPI (SYNCHRONOUS PERIPHERAL INTERFACE)
uPSD33xx devices support one serial SPI inter-
face in Master Mode only. This is a three- or four-
wire synchronous communication channel, capa-
ble of full-duplex operation on 8-bit serial data
transfers. The four SPI bus signals are:
■ SPIRxD
Pin P1.5 or P4.5 receives data from the Slave
SPI device to the uPSD33xx
■ SPITxD
Pin P1.6 or P4.6 transmits data from the
uPSD33xx to the Slave SPI device
■ SPICLK
Pin P1.4 or P4.4 clock is generated from the
uPSD33xx to the SPI Slave device
This SPI interface supports single-Master/multi-
ple-Slave connections. Multiple-Master connec-
tions are not directly supported by the uPSD33xx
(no internal logic for collision detection).
If more than one Slave device is required, the
SPISEL signal may be generated from uPSD33xx
GPIO outputs (one for each Slave) or from the
PLD outputs of the PSD Module. Figure 41. illus-
trates three examples of SPI device connections
using the uPSD33xx:
■ Single-Master/Single-Slave with SPISEL
■ Single-Master/Single-Slave without SPISEL
■ Single-Master/Multiple-Slave without SPISEL
■ SPISEL
Pin P1.7 or P4.7 selects the signal from the
uPSD33xx to an individual Slave SPI device
Figure 41. SPI Device Connection Examples
uPSD33xx
SPI Master
SPIRxD
SPITxD
SPICLK
SPISEL
SPI Bus
MISO
MOSI
SCLK
SS
SPI Slave
Device
uPSD33xx
SPI Master
SPIRxD
SPITxD
SPICLK
SPI Bus
MISO
MOSI
SCLK
SS
SPI Slave
Device
Single-Master/Single-Slave, with SPISEL
Single-Master/Single-Slave, without SPISEL
SPIRxD
SPITxD
SPICLK
GPIO or PLD
uPSD33xx
SPI Master
SPI Bus
GPIO or PLD
MISO
MOSI
SCLK
SS
MISO
MOSI
SCLK
SS
SPI Slave
Device
SPI Slave
Device
Single-Master/Multiple-Slave, without SPISEL
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