UPSD33XX Datasheet, PDF (178/231 Pages) STMicroelectronics – Fast 8032 MCU with Programmable Logic

uPSD33xx
Peripheral I/O Mode. This mode will provide a
data bus repeater function for the 8032 to interface
with external parallel peripherals. The mode is
only available on Port A (80-pin devices only) and
the data bus signals, D0 - D7, are de-multiplexed
(no address A0-A7). When active, this mode be-
haves like a bidirectional buffer, with the direction
automatically controlled by the 8032 RD and WR
signals for a specified address range. The DPLD
signals PSEL0 and PSEL1 determine this address
range. Figure 69., page 169 shows the action of
Peripheral I/O mode on the Output Enable logic of
the tri-state output driver for a single port pin. Fig-
ure 73., page 178 illustrates data repeater the op-
eration. To activate this mode, choose the pin
function “Peripheral I/O Mode” in PSDsoft Express
on any Port A pin (all eight pins of Port A will auto-
matically change to this mode). Next in PSDsoft,
specify an address range for the PSELx signals in
the “Chip-Select” section of the “Design Assistant.”
Specify an address range for either PSEL0 or
Figure 73. Peripheral I/O Mode
8032 RD
PSEL1. Always qualify the PSELx equation with
“PSEN is logic '1'” to ensure Peripheral I/O mode
is only active during 8032 data cycles, not code cy-
cles. Only one equation is needed since PSELx
signals are OR’ed together (Figure 73). Then in
the 8032 initialization firmware, a logic ’1’ is written
to the csiop VM register, Bit 7 (PIO_EN) as shown
in Table 73., page 132. After this, Port A will auto-
matically perform this repeater function whenever
the 8032 presents an address (and memory page
number, if paging is used) that is within the range
specified by PSELx. Once Port A is designated as
Peripheral I/O mode in PSDsoft Express, it cannot
be used for other functions.
Note: The user can alternatively connect an exter-
nal parallel peripheral to the standard 8032 AD0-
AD7 pins on an 80-pin uPSD device (not Port A),
but these pins have multiplexed address and data
signals, with a weaker fanout drive capability.
PSEL0
PSEL1
VM REGISTER BIT 7 (PIO EN)
8032 DATA
BUS D0-D7 8
(DE-MUXED)
PA0 - PA7
8 _PORT
A pins
8032 WR
AI02886A
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