GDC21D601 Datasheet, PDF (91/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
2. Signal Description
The RTC module is connected to the APB bus. Table 1. APB signal descriptions describes the APB signals used
and produced.
NAME
PCLK
P_A[4:2]
P_D[31:0]
P_STB
P_WRITE
P_SEL
BnRES
RTCIRQ
Table 1. APB Signal Descriptions
TYPE
I
I
I/O
I
I
I
I
O
SOURCE/
DESTINATION
Power
Management
Unit
APB Bridge
APB
Peripherals,
B_D bus
APB Bridge
APB Bridge
APB Bridge
Power
Management
Unit
Interrupt
Controller
DESCRIPTION
The slow APB clock used to re-synchronize data is transferred
between the 32.768KHz clock and the APB.
This is the peripheral address bus, which is used by an individual
peripheral for decoding register accesses to this peripheral.
The addresses become valid before P_STB goes to HIGH and remain
valid after P_STB goes to LOW.
This is the bi-directional peripheral data bus. The data bus is driven
by this block during read cycles (when P_WRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of P_STB is coincident with the falling edge of
B_CLK.
When this signal is HIGH, it indicates a write to a peripheral. When
this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before P_STB goes to HIGH and remains valid after
P_STB goes to LOW.
When this signal is HIGH, it indicates that this module has been
selected by the APB bridge. This selection is a decode of the system
address bus (ASB). See AMBA Peripheral Bus Controller for more
details.
Reset signal generated from the PMU
Interrupt signal to the Interrupt module. When this signal is HIGH, it
indicates a valid comparison between the counter value and the match
register. It also indicates 1Hz interval with enable bit in control
register.
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