GDC21D601 Datasheet, PDF (75/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Reset Status Register (RSTSR)
Two-bit read only register. The RSTSR indicates whether TCNT is overflowed or not. The RSTSR is initialized to
0x0 by the reset signal, nB_RES.
Bit 0 (WTOVF) indicates that the TCNT has overflowed in the watchdog timer mode. Bit 1 (ITOVF) indicates that
the TCNT has overflowed in the interval timer mode.
Table 5. SR Bit Description
BIT
INITIAL
VALUE
0 (watchdog timer overflow flag : WTOVF) 0
1 (interval timer overflow flag : ITOVF)
0
FUNCTION
indicate that the TCNT has overflowed in the
watchdog timer mode.
indicate that the TCNT has overflowed in the
interval timer mode
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