GDC21D601 Datasheet, PDF (111/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
2. Signal Description
The PIO module is connected to the APB bus. Table 1. Signal descriptions describe the APB signals used and
produced. Table 2. Specific block signal descriptions show the non-AMBA signals from the block.
NAME
BnRES
PA[7:2]
PD[7:0]
PSTB
PWRITE
PSEL
Table 1. Signal Descriptions
TYPE
I
I
I/O
I
I
I
SOURCE/
DESTINATION
PMU
APB Bridge
APB
Peripherals, BD
bus
APB Bridge
APB Bridge
APB Bridge
DESCRIPTION
This signal indicates a power on reset status of the bus (active LOW).
This is the part of the peripheral address bus, which is used by the
peripheral for decoding its own register accesses.
The addresses become valid before PSTB goes to HIGH and remain
valid after PSTB goes to LOW.
This is the part of the bi-directional peripheral data bus. The data bus is
driven by this block during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of PSTB is coincident with the falling edge of BCLK
(ASB system clock).
When this signal is HIGH, it indicates a write to a peripheral and when
this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes to HIGH and remains valid after
PSTB goes to LOW.
When this signal is HIGH, it indicates the PIO module has been
selected by the APB bridge. This selection is a decode of the system
address bus (ASB). For more details, see AMBA Peripheral Bus
Controller
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