GDC21D601 Datasheet, PDF (68/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
2. Hardware Interface and Signal Description
The Watchdog Timer module is connected to the APB bus.
NAME
B_CLK
P_A[4:2]
P_D[7:0]
P_STB
P_WRITE
P_SEL
nB_RES
INT_WDT
MNRST
PORST
Table 1. APB Signal Descriptions
Type
I
I
I/O
I
I
I
I
O
O
O
SOURCE/
DESTINATION
DESCRIPTION
Clock controller System (bus) clock. This clock times all bus transfers. The clock has
two distinct phases - phase 1 when B_CLK is LOW, and phase 2
when B_CLK is HIGH.
APB Bridge
This is the peripheral address bus used by an individual peripheral for
decoding register accesses to that peripheral.
The addresses become valid before P_STB goes to HIGH and remain
valid after P_STB goes to LOW.
APB Peripherals, This is the bi-directional peripheral data bus. The data bus is driven
B_D bus
by this block during read cycles (when P_WRITE is LOW).
APB Bridge
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of P_STB is coincident with the falling edge of
B_CLK.
APB Bridge
When this signal is HIGH, it indicates a write to a peripheral. When
LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before P_STB goes to HIGH and remains valid after
P_STB goes to LOW.
APB Bridge
When this signal is HIGH, it indicates that this module has been
selected by the APB bridge. This selection is a decode of the system
address bus (ASB). See AMBA Peripheral Bus Controller for more
details.
Power
Reset signal generated from the APB Bridge
Management Unit
Interrupt
When this signal is HIGH, it indicates that a system becomes
Controller
uncontrolled, and the timer counter overflows without being rewritten
correctly by the CPU or it overflows in the interval timer mode.
Power
When this signal is HIGH, this signal indicates that the manual reset
Management Unit signal has selected as the internal reset signal, and the timer counter
overflows without being rewritten correctly by the CPU or it
overflows in the interval timer mode..
Power
When this signal is HIGH, this signal indicates that the power-on
Management Unit reset signal has selected as the internal reset signal.
Writes to the Watchdog Timer module are generated from the Peripheral Bus Controller module. Figure 2.
Watchdog timer module APB write cycle summarizes this description.
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