GDC21D601 Datasheet, PDF (135/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Interrupt Identification Register
In order to provide minimum software overhead during data character transfers, the UART prioritizes interrupts
into four levels and records them in the Interrupt Identification Register. The four levels of interrupt conditions are
as follows in order of priority :
• Receiver Line Status
• Received Data Ready
• Transmitter Holding Register Empty
• MODEM Status
When the CPU accesses the IIR, the UART freezes all interrupts and indicates the highest priority pending
interrupt to the CPU. While this CPU access occurs, the UART records new interrupts, but does not change its
current indication until the access is complete. Table 5. Summary of Registers shows the contents of the IIR.
Details on each bit are :
Bit 0 :
This bit can be used in a prioritized interrupt environment to indicate whether an interrupt is
pending or not. When bit 0 is a logic 0, an interrupt is pending and the IIR contents may be used as
a pointer for the appropriate interrupt service routine. When bit 0 is a logic 1, no interrupt is
pending.
Bit 1 and 2 : These two bits of the IIR are used to identify the highest priority interrupt pending as indicated in
Table 9. Interrupt control functions.
Bit 3 :
In the 16450 mode this bit is 0. In the FIFO mode this bit is set along with bit 2 when a time-out
interrupt is pending.
Bit 4 and 5 : These two bits of the IIR are always logic 0.
Bit 6 and 7 : These two bits are set when FCR0 = 1.
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