GDC21D601 Datasheet, PDF (33/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
4. Register Description
4.1 Memory Map
The base address (=DRAM REG Base) of the DRAM controller register bank is 0xFFFFED00.
Table 5. Memory Map of the Dram Controller Peripheral
ADDRESS
Base + 0x0
Base + 0x4
Base + 0x8
Base + 0xC
WRITE LOCATION
DRAM Refresh Control Register (RCR)
DRAM Control Register for CPU
DRAM Control Register for DMA
DRAM Test Control Register (TCR)
READ LOCATION
N/A
DRAM Control Register for CPU
DRAM Control Register for DMA
N/A
INITIAL
16’h0000
7’b0000000
6’b000000
4’b0000
4.2 DRAM Refresh Control Register(RCR)
The DRAM refresh period register is an 16-bit write register which enables the refresh and selects the refresh
period used by the DRAM controller for its periodic CAS-before-RAS refresh. The value in the DRAM refresh
period register is only cleared by a Power On Reset (BnRES = 0).
15
8
7
6
REFCNT
RFSHEN
0
RFDIV
Figure 7. DRAM Controller Refresh Register
REFCNT DRAM Refresh Clock Divisor. Refresh Clock is setting by this bit field :
RefClock = BCLK/REFCNT
The REFCNT field should not be programmed with zero since this results in no initiated refresh
cycles.
RFSHEN DRAM refresh enable. Setting this bit enables periodic refresh cycles to be generated by the DRAM
controller at the rate set by the RFDIV field. Setting this bit also enables self-refresh mode when the
DRAM controller is in the power down state.
RFDIV This 7-bit field sets the DRAM refresh rate. The refresh period is deriven from internally generated
clock and is given by the following formula:
Frequency (KHz) = 2*[RefClock /(RFDIV + 1)]
or
RFDIV = ( RefClock / 0.5*Refresh frequency (KHz) ) - 1
The RFDIV field should not be programmed with zero since this results in no initiated refresh cycles.
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