GDC21D601 Datasheet, PDF (117/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Section 14. Synchronous Serial Peripheral Interface
1. General Description
The synchronous serial interface (SSPI) is a high-speed synchronous serial I/O system. The SSPI can be used for
simple I/O expansion or for allowing several MCUs to be interconnected in a multi-master configuration. Clock
polarity, clock phase, chip select polarity, and MSB /LSB first ordering are software programmable to allow direct
compatibility with a large number of peripheral devices. The SSPI system can be configured as either a master or a
slave.
From
ASB
BnRES
PSEL
PSTB
From/to
APB
PWRITE
PA[5:2]
PD[7:0]
PCLK
From
clock
generator
SSPI IRQ
To Interrupt Controller
SSICS
APB
INTERFACE
clock
scaler
SSCR0
SSCR1
SSSR
SSDR
SSTR
Tx
16*8 FIFO
Rx
16*8 FIFO
SSIOUT
SSIIN
SSICLK
Figure 1. Signal Connections of the SSPI
An 8-bit shift register feeds the output channel, SSIOUT. During transfers, the BUSY bit in the system status
register SSSR is set. Valid data can be read from a 16-bit shift register when the BUSY bit is cleared. There is also
an interrupt signal, SSIIRQ, which is asserted at the end of data transfer. Reading data clears the interrupt signal.
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