GDC21D601 Datasheet, PDF (35/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
4.4 DRAM Control Register for DMA
This Register controls the DRAM control signals when DRAM accessed by DMA.
Setting the register is effective only when the DMAEn bit set by DRAMConCPU(DRAM Control register from
CPU).
15
6
5
4
3
2
1
0
Reserve
TRP
TCP
WaitCnt
BankSize
Figure 9. DRAM Control Register for DMA (DRAMConDMA)
4.5 DRAM Test Control(TCR)
The DRAM test control register is for test and should not be used during normal operation. It is a write-only
register with the following format.
15
4
Reserved
3
TESTINC
2
FORCEADV
1
0
FORCESIZE
Figure 10. DRAM Test Control Register
TESTINC
Test increment (TESTINC). This bit puts the column address increment into a test mode. In
this mode each nibble of the column address increment increments independently. Resets it to
0.
FORCEADV
Force refresh advance (FORCEREFADV). This bit forces the refresh counter to advance every
BCLK. Resets it to 0.
FORCESIZE[1:0] Force access size. These bits force the size of accesses to the DRAM bank. When this is set to
10 (default), the ASB B_SIZE is used to determine the size of the access. When this is set to
00 or 01, a byte or half-word access is forced respectively. Resets it to 10.
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