GDC21D601 Datasheet, PDF (188/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

UART Register (@0xFFFF F500) -- Continued
ABBREVIATION
MCR
LSR
MSR
SCR
ADDRESS
0xFFFFF510
0xFFFFF514
0xFFFFF518
0xFFFFF51C
DESCRIPTIONS
MODEM Control Register
Bit 7-5 : Reserved
Bit 4 : Loop control
Bit 3,2 : Reserved
Bit 1 : RTS
Bit 0 : DTR
Line Status Register
Bit 7 : Rx FIFO Error
Bit 6 : Transmitter Empty
Bit 5 : THR Empty
Bit 4 : Break Interrupt
Bit 3 : Framming Error
Bit 2 : Parity Error
Bit 1 : Overrun Error
Bit 0 : Data Ready
MODEM Status Register
Bit 7 : DCD(Data Carrier Detect)
Bit 6 : RI(Ring Indicator)
Bit 5 : DSR(Data Set Ready)
Bit 4 : CTS(Clear To Send)
Bit 3 : DDCD(Delta Data Carrier Detec)
Bit 2 : TERI(Trailing Edge Ring Indi.)
Bit 1 : DDSR(Delta Data Set Ready)
Bit 0 : DCTS(Data Clear To Send)
Scratch Register
GDC21D601
R/W INITIAL VALUE
R/W 8b’00000000
R/W 8b’01100000
R/W 8b’xxxx0000
R/W 8b’10011000
189