GDC21D601 Datasheet, PDF (112/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
Table 2. Specific Block Signal Descriptions
NAME
PA[7:0]
EPA[7:0]
PAOE[7:0]
PB[7:0]
EPB[7:0]
PBOE[7:0]
PC[7:0]
EPC[7:0]
PCOE[7:0]
PD[7:0]
EPD[7:0]
PDOE[7:0]
PE[7:0]
EPE[7:0]
PEOE[7:0]
PF[7:0]
EPF[7:0]
PFOE[7:0]
PG[7:0]
TYPE
O
I
O
O
I
O
O
I
O
O
I
O
O
I
O
O
I
O
Out
SOURCE/
DESTINATION
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
PADS
DESCRIPTION
Port A output driver. Values written on PADR register are put onto
these lines and driven out to the port A pins if the corresponding data
direction bits are set to HIGH (PADDR register).
Port A input driver. It reflects the external state of the port. This
information is obtained when the PADR register is read.
Port A output enable (active LOW). Values written on PADDR
register are put onto these lines.
Port B output driver. Values written on PBDR register are put onto
these lines and driven out to the port A pins if the corresponding data
direction bits are set to HIGH (PBDDR register).
Port B input driver. It reflects the external state of the port. This
information is obtained when the PBDR register is read.
Port B output enable (active LOW). Values written on PBDDR register
are put onto these lines.
Port C output driver. Values written on PCDR register are put onto
these lines and driven out to the port A pins if the corresponding data
direction bits are set HIGH (PCDDR register).
Port C input driver. It reflects the external state of the port. This
information is obtained when the PCDR register is read.
Port C output enable (active LOW). Values written on PCDDR register
are put onto these lines.
Port D output driver. Values written on PDDR register are put onto
these lines and driven out to the port D pins if the corresponding data
direction bits are set to HIGH (PDDDR register).
Port D input driver. It reflects the external state of the port. This
information is obtained when the PDDR register is read.
Port D output enable (active LOW). Values written on PDDDR
register are put onto these lines.
Port E output driver. Values written on PEDR register are put onto
these lines and driven out to the port E pins if the corresponding data
direction bits are set to HIGH (PEDDR register).
Port E input driver. It reflects the external state of the port. This
information is obtained when the PEDR register is read.
Port E output enable (active LOW). Values written on PEDDR register
are put onto these lines.
Port F output driver. Values written on PFDR register are put onto
these lines and driven out to the port F pins if the corresponding data
direction bits are set to HIGH (PFDDR register).
Port F input driver. It reflects the external state of the port. This
information is obtained when the PFDR register is read.
Port F output enable (active LOW). Values written on PFDDR register
are put onto these lines.
Port G output driver. Values written on PGDR register are put onto
these lines and driven out to the port G pins if the corresponding data
direction bits are set to HIGH (PGDDR register).
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