GDC21D601 Datasheet, PDF (29/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
BCLK
DRAMA[12:0]
nRAS[1:0]
nCAS[1:0]
XData[31:0]
nOE
nWE
row
col
row col1 col2 col3
Data
Data1 Data2 Data3
Figure 3. DRAM External Signal Timing: Write Cycles
BCLK
nRAS[1:0]
nCAS[1:0]
nOE
nWE
Figure 4. DRAM Controller Refresh Cycle
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