GDC21D601 Datasheet, PDF (25/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

3. Core Block Diagram
A [31:0]
ALE
ABE
Address Register
P
C
b
u
Address
Incrementer
s
A
L
Register Bank
(31 x 32-bit registers)
U
(6 status registers)
b
u
s
A
b
u
s
32 x 8
Multiplier
Barrel Shifter
32-bit ALU
Scan
I Control
n
c
r
e
m
e
n
t
e
Instruction
r _Decoder
b
&
u _Control
s
Logic
B
b
u
s
DBGRQI
BREAKPTI
DBGACK
ECLK
nEXEC
ISYNC
BL [3:0]
APE
MCLK
nWAIT
nIRQ
nFIQ
nRESET
ABORT
SEQ
LOCK
nCPI
CPA
CPB
nM [4:0]
TBE
TBIT
HIGHZ
Write Data Register
Instruction Pipeline
& Read Data Register
& Thumb Instruction Decoder
nENOUT DBE nENIN
D [31:0]
Core
GDC21D601
ScanChain2
ICE
Breaker
RANGEOUT0
RANGEOUT1
ESTERN1
EXTERN0
nRW
MAS [1:0]
nTRANS
nMREQ
nOPC
A [0:31]
Bus
Splitter
D [0:31]
DIN [0:31]
DOUT [0:31]
Scan
Chain 0
Scan
Chain 1
TAP Controller
SCREG [3:0]
IR [3:0] TASPM [3:0]
TDO TDI nTRST TMS TCK
Figure 2. ARM7TDMI Core Block Diagram
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