GDC21D601 Datasheet, PDF (48/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
3. Register Description
3.1 Register Memory Map
The base address of MCU control Register is 0xFFFFEB00.
ADDRESS
MCURegBase + 0x0000
MCURegBase + 0x0004
MCURegBase + 0x0008
MCURegBase + 0x000C
MCURegBase + 0x00010
MCURegBase + 0x00014
MCURegBase + 0x00018
MCURegBase +0x0001C
MCURegBase + 0x00020
MCURegBase + 0x00024
MCURegBase + 0x00028
MCURegBase +0x0002C
MCURegBase + 0x00030
MCURegBase + 0x00034
Table 2. MCU Controller Memory Map
R/W
INITIAL
VALUE
DESCRIPTION
R/W
0x00 MCU Control Register
R/W
0x00 PINMUX_PA Register, Multi-function pin MUX Control
signals for Port A[5:0]
R/W
0x00 PINMUX_PB Register, Multi-function pin MUX Control
signals for Port B[7:0]
R/W
0x00 PINMUX_PC Register, Multi-function pin MUX Control
signals for Port C[7:0]
R/W
0x00 PINMUX_PD Register, Multi-function pin MUX Control
signals for Port D[7:0]
R/W
0x00 PINMUX_PE Register, Multi-function pin MUX Control
signals for Port E[8:0]
R/W
0x00 PINMUX_PF Register, Multi-function pin MUX Control
signals for Port F[8:0]
R/W
0x00 PINMUX_PG Register, Multi-function pin MUX Control
signals for Port G[7:0]
R/W
0x00 PINMUX_PH Register, Multi-function pin MUX Control
signals for Port H[7:0]
R/W
0x00 PINMUX_PI Register, Multi-function pin MUX Control
signals for Port I[7:0]
R/W
0x00 PINMUX_PJ Register, Multi-function pin MUX Control
signals for Port J[7:0]
R
$LG601 MCU Device Code Register
R
0x0 DRAM Power Down Ack
W
0x0
DRAM Power Down Req
3.2 MCUC_CON Register
31
Reserved
2
Ari_Pri
1
Isram
0
Drambank0
drambank0
Isram
Ari_pri
When this register is HIGH, DRAM memory address bank #0 area is located at 0.
When this register is HIGH, On-Chip SRAM address area is located at 0
Arbiter Priority control signal. See also Section 2 System Architecture for details.
Figure 1. MCU Controller Register
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