GDC21D601 Datasheet, PDF (28/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
NAME
NDRAMALatch
DRAMA[12:0]
NDRAMInEn
NDRAMInLEn[3:0]
NDRAMOutEn
NDRAMOutLen
DESCRIPTION
DRAM Address Latch. When this signal is LOW, it opens the EBI address latch. This
signal is HIGH when DRAM operations do not occur. This signal provides support for a
shared EBI and may not be needed in a system where the DRAM controller does not share
the EBI with other memory controllers.
These multiplexed address lines are connected to the DRAM Address.
DRAM Input Enable. When this signal is LOW, it enables the EBI drivers from latched XD
to BD. This signal is HIGH when DRAM read operations are not performed.
DRAM Input Latch Enable. When this signal is HIGH, it shuts the EBI latches on XD. This
signal is LOW when DRAM read operations are not performed.
DRAM Output Enable. When this signal is HIGH, it disables the EBI drivers from latched
BD to XD. This signal is low when DRAM write operations are not performed.
DRAM Output Latch Enable. When this signal is LOW, it opens the EBI latches on BD.
This signal is HIGH when DRAM write operations are not performed.
Accesses to the DRAM Controller module are generated as a result of the address decode put out on the ASB
address bus by the current bus master (which could be the ARM CPU or the DMA engine, for example).
The following three diagrams show the timing of the external interface for read, write and refresh cycles
(Figure 2, 3, 4).
BCLK
DRAMA[12:0]
nRAS[1:0]
nCAS[1:0]
XData[31:0]
nOE
nWE
row col
row col1 col2 col3
Figure 2. DRAM External Signal Timing: Read Cycles
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