GDC21D601 Datasheet, PDF(116/189 Page) Hynix Semiconductor

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GDC21D601 Datasheet, PDF (116/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

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GDC21D601

5. Programmerâ s Model

5.1 PIO Registers

The following user registers are provided:

PnDR

Port n Data Register. Values written to this 8-bit read/write register will be output on port A pins if the

corresponding data direction bits are set to HIGH (port output). Values read from this register reflect

the external states of port n, not necessarily the value should be written to it. All bits are cleared by a

system reset.

PnDDR

Port n Data Direction Register. Bits set in this 8-bit read/write register will select the corresponding

pins in port n to become an output, clearing a bit sets the pin to input. All bits are cleared by a system

reset.

n : A, B, C, D, E, F, G, H, I and J

5.2 Register Memory Map

The base address of the PIO is 0xFFFF FC00 and the offset of any particular register from the base address is

determined.

ADDRESS

PIO Base + 0x00

PIO Base + 0x04

PIO Base + 0x08

PIO Base + 0x0c

PIO Base + 0x10

PIO Base + 0x14

PIO Base + 0x18

PIO Base + 0x1c

PIO Base + 0x20

PIO Base + 0x24

PIO Base + 0x28

PIO Base + 0x2c

PIO Base + 0x30

PIO Base + 0x34

PIO Base + 0x38

PIO Base + 0x3c

PIO Base + 0x40

PIO Base + 0x44

PIO Base + 0x48

PIO Base + 0x4c

Table 3. PIO Register Memory Map

READ LOCATION

PADR register

PADDR register

PBDR register

PBDDR register

PCDR register

PCDDR register

PDDR register

PDDDR register

PEDR register

PEDDR register

PFDR register

PFDDR register

PGDR register

PGDDR register

PHDR register

PHDDR register

PIDR register

PIDDR register

PJDR register

PJDDR register

WRITE LOCATION