GDC21D601 Datasheet, PDF (187/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

SSPI Register (@ 0xFFFF F800) -- Continued
ABBREVIATION
SSDR1
SSSR1
SSTR1
ADDRESS
0xFFFFF828
0xFFFFF82C
0xFFFFF830
DESCRIPTIONS
SSPI 1 Data Register
SSPI 1 Status Register
Bit 7 : Rx FIFO Empty
Bit 6 : Tx FIFO Empty
Bit 5 : Rx FIFO FULL
Bit 4 : Tx FIFO FULL
Bit 3 : Tx END
Bit 2 : Reserved
Bit 1 : Reserved
Bit 0 : SSPI BUSY
SSPI 0 Term Register
GDC21D601
R/W INITIAL VALUE
R/W 8b’11111111
R 8b’00000000
W 8b’11111111
UART Register (@0xFFFF F500)
ABBREVIATION
RBR0
THR
DLL
DLM
IER
ADDRESS
0xFFFFF500
0xFFFFF504
IIR / FCR
0xFFFFF508
LCR
0xFFFFF50C
DESCRIPTIONS
Receiver Buffer Register
(DLAB=0)
Transmitter Holding Register (DLAB=0)
Divisor Latch LS
(DLAB=1)
Divisor Latch MS
(DLAB=1)
Interrupt Enable Register
Bit 7-4 : Reserved
Bit 3 : Modem status interrupt
Bit 2 : Receiver line status interrupt
Bit 1 : THR empty interrupt
Bit 0 : Rx data available interrupt
Interrupt Identification Register
FIFO Control Register
Bit 7 : RCVR Trigger to MSB
Bit 6 : RCVR Trigger to LSB
Bit 5-3 : Reserved
Bit 2 : XMIT FIFO Reset
Bit 1 : RCVR FIFO Reset
Bit 0 : FIFO Enable
Line Control Register
Bit 7 : DLAB (Divisor Latch Access Bit)
Bit 6 : Break control bit
Bit 5 : Stick parity bit
Bit 4 : Even parity control
Bit 3 : Parity Control (0: Disabled)
Bit 2 : Stop bit(s)
(0: Disabled)
Bit 1,0 : character bits
00(5-bit),01(6-bit), 10(7-bit), 11(8-bit)
R/W INITIAL VALUE
R 8b’10011000
W 8b’10011000
R/W 8b’10011000
R/W 8b’10011000
R/W 8b’00000000
R 8b’00000001
W
R/W 8b’00000000
188