GDC21D601 Datasheet, PDF (139/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR 0 = 1, IER 0 = 1), RCVR interrupts occur as
follows :
1. The received data available interrupt will be issued to the CPU when the FIFO has reached its programmed
trigger level; it will be cleared as soon as the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR-06), as before, has higher priority than the received data available(IIR-04)
interrupt.
4. The data ready bit (LSR 0) is set as soon as a character is transferred from the shift register to the RCVR FIFO.
It is reset when the FIFO is empty.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO timeout interrupts occurs as follows :
1. A FIFO timeout interrupt occurs in the following conditions :
- at least one character is in the FIFO
- the latest serial character received was longer than 4 continuous character times (if 2 stop bits are programmed,
the second one is included in this time delay).
- the latest CPU read of the FIFO was longer than 4 continuous character times.
This will cause a maximum character received to interrupt issued delay of 160 ms at 300 baud with a 12 bit
character.
2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay proportional to
the baud rate).
3. When a timeout interrupt has occurred, it is cleared and the timer is reset when the CPU reads one character
from the RCVR FIFO.
4. When a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the
CPU reads the RCVR FIFO.
When the XMIT FIFO and transmitter interrupts are enabled (FCR 0 = 1, IER 1 = 1), XMIT interrupts occur as
follows :
1. The transmitter holding register interrupt (02) occurs when the XMIT FIFO is empty; it is cleared as soon as the
transmitter holding register is written to (1 to 16 characters may be written to the XMIT FIFO while this
interrupt is serviced or the IIR is read.
2. The transmitter FIFO empty indications will be delayed 1 character time minus the last stop bit time whenever
the following occurs: THRE = 1 and there has not been at least two bytes at the same time in the transmit FIFO
since the last THRE = 1. The first transmitter interrupt affect changing FCR 0 will be immediate if it is enabled.
Character timeout and RCVR FIFO trigger level interrupts have the same priority as the current received data
available interrupt; XMIT FIFO empty has the same priority as the current transmitter holding register empty
interrupt.
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