GDC21D601 Datasheet, PDF (140/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
FIFO Polled Mode Operation
When FCR 0 = 1 resetting, IER 0, IER 1, IER 2, IER3 or all to zero puts the UART in the FIFO Polled Mode.
Since the RCVR and XMITTER are controlled separately, either one or both can be in the polled mode of
operation.
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