GDC21D601 Datasheet, PDF (74/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
6. Watchdog Timer Register Descriptions
The following registers are provided for watchdog timer:
Timer Counter (TCNT)
8-bit readable and writable upcounter. When the timer is enabled, the timer counter starts counting pulse of the
selected clock source. When the value of the TCNT changes from 0xFF-0x00(overflows), a watchdog timer
overflow signal is generated in the both timer modes. The TCNT is initialized to 0x00 by a power-reset(nB_RES).
Timer/Reset Control Register (TRCR)
8-bit readable and writable register. The following functions are provided :
Selecting the timer mode
Selecting the internal clock source
Selecting the reset mode
Setting the timer enable bit
Being enable interrupt request
Being enable reset signal occurrence
The clock signals are obtained by dividing the frequency of the system clock.
Table 4. TRCR Bit Description
BIT
0 (clock select : CKS0)
INITIAL
VALUE
0 000 = /2
1 (clock select : CKS1)
2 (clock select : CKS2)
3 (reset select : RSTSEL)
0 001 = /8
0 010 = /32
011 = /64
100 = / 256
101 = /512
110 = /2048
111 = /8192
0 0 = poser-on reset
1 = manual reset
4 (reset enable : RSTEN)
0 0 = disable
1 = enable
5 (timer enable : TMEN)
0 0 = disable
1 = enable
6 (timer mode select : WT/nIT)
0
0 = interval timer mode
1 = watchdog timer mode
7 (Interrupt enable : INTEN)
0 0 = disable
1 = enable
FUNCTION
select one of eight internal clock
sources for input to the TCNT.
select the type of generated internal
reset if the TCNT overflows in the
watchdog timer mode.
select whether to reset the chip
internally or not if the TCNT overflows
in the watchdog timer mode.
enable or disable the timer
select whether to use the WDT as a
watchdog timer or interval timer
enable or disable the interrupt request
75