GDC21D601 Datasheet, PDF (128/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

4. Internal Block Diagram
P_D[7:0]
DATA
BUS
BUFFER
P_A[0]
P_A[1]
P_A[2]]
P_SEL
P_WRITE
P_STB
U_CLK
APB I/F
&
CONTROL
LOGIC
nB_RES[0]
RECEIVER
BUFFER
REGISTER
LINE
CONTROL
REGISTER
DIVISOR
LATCH(LS)
DIVISOR
LATCH(MS)
RECEIVER
FIFO
BAUD
GENERATOR
LINE
STATUS
REGISTER
TRANSMITTER
HOLDING
REGISTER
TRANSMITTER
FIFO
MODEM
CONTROL
REGISTER
MODEM
STATUS
REGISTER
INTERRUPT
ENABLE
REGISTER
INTERRUPT
ID
REGISTER
INTERRUPT
CONTROL
LOGIC
FIFO
CONTROL
REGISTER
Figure 1. Internal Block Diagram
GDC21D601
RECEIVER
SHIFT
SIN
REGISTER
RECEIVER
TIMING
&
CONTROL
TRANSMITTER
TIMING
&
CONTROL
TRANSMITTER
SHIFT
REGISTER
SOUT
MODEM
CONTROL
LOGIC
nRTS
nCTS
nDTR
nDSR
nDCD
nRI
INT_UART
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