GDC21D601 Datasheet, PDF (121/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
SSSR SS Status Register. This is automatically set when data transfer is complete between processor and
external device. The flag is cleared by a read of SSSR followed by a read or write of SSDR.
SSTR SS Term Register. This is a register, which has a term between this byte and next byte by user’s setting.
The value can be 0 through 255. This is used only when master mode.
Table 4. SSSR Registers (Read)
BIT
NAME
7
RX fifo empty
6
TX fifo empty
5
RX fifo full
4
TX fifo full
3
TX end
2
R
1
R
0
BUSY
FUNCTION
Active high
Active high
Active high
Active high
Active high
Reserved
Reserved
when SSI transmitting and receiving
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