GDC21D601 Datasheet, PDF (150/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

4.1 Master Transmitter Sequence
• Step 1 : read status register. Check if bbusy is
cleared
• Step 2 : write slave address to data register
write 5’b10111 to control register
• Step 3 : wait for interrupt
write 5’bx0011 to control register
• Step 4 : read status register. Check blost, ack_rpy
4.2 Master Receiver Sequence
• Step 1 : read status register.
Check if bbusy is cleared
• Step 2 : write slave address to data register
write 5’b10111 to control register
• Step 3 : wait for interrupt
read status register. Check blost, ack_rpy
if blost is 1, go to step 1.
else if ack_rpy is 1, go to step 5.
GDC21D601
if blost is 1, go to step 1.
else if ack_rpy is 1 go to step 6.
• Step 5 : write data to transmit register
if this data is the last, go to step 6.
wait for interrupt. Go to step 4.
• Step 6 : write 5’b11011 to control register
write 5’b10001 to control register
write 0xff to transmit register
• Step 4 : if this data is the last, go to step 5.
wait for interrupt
read data from data register
read status register. Check ack_rpy
if ack_rpy is 0 go to step 4.
• Step 5 : write 5’b11011 to control register
5. I²C Restart Capability (Combined Mode)
The I²C controller can restart without going to STOP condition. If a I²C master wants to restart after
sending/receiving 1 byte data , just keep the start_ctrl and ack_ctrl bit in ctrl_r, and if a master wants to restart after
sending/receiving several bytes data, set start_ctrl and ack_ctrl bit in ctrl_r just before sending/receiving last data.
The followings shows the restart operation after transfer 1 byte. It sets start_ctrl and ack_ctrl to 1 at first interrupt.
1. read status register. Check if bbusy is cleared
2. write slave address to data register
write 5’b10111 to control register
3. wait for interrupt
read status register. Check ack_rpy
if ack_rpy is 1, go to step 5.
else write 5’b10111 to control register
to restart
4. wait for interrupt.
Write slave address to data register.
Write 5’b10001 to control register.
5. wait for interrupt
if this data is the last, go to step 6.
read status register. Check ack_rpy
if ack_rpy is 0 go to step 5.
6. write 5’b11011 to control register
If above data transfer is transmitter, write data to transmit register else if recevier write 8’hff to transmit register.
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