GDC21D601 Datasheet, PDF (149/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

2. I²C Controller Key Features
The I²C controller contains the following key features:
• Two-Wire Interfaces (SDA and SCL)
• Both Master and Slave functions
• Supports Clock Rates up to 400khz in Master Mode .
• Independent Programmable Baud Rate Generator
• Local Loopback Capability for Testing
• Slave clock stretching support
GDC21D601
3. I²C Controller Clocking and Pin Functions
The I²C controller can be configured as a master or slave for the serial channel.
When the I²C controller is a master, the I²C controller baud rate generator is used to generate the I²C controller
transmit and receive clocks. The I²C baud rate generator takes its input from the block clock input.
Both serial data (SDA) and serial clock (SCL) are bi-directional pins. These pins are connected to a positive supply
voltage via an external pull up resister. When the bus is free, both lines are high.
When the I²C controller is working as a master, SCL is the clock output signal that shifts the received data in and
shifts the transmit data out from/to the SDA pin.
When the I²C controller functions as a slave, its internal clock is synchronized by the incoming clock from SCL
line.
4. I²C Master Mode Transmit / Receive Process
When the I²C controller functions in master mode, the I²C master initiates a transaction by transmitting a message
to the peripheral (I²C slave) as a transmitter mode. The message specifies a read or write operation. If a read
operation is specified, the direction of the transfer is changed at the moment of the first acknowledge, and the
called slave receiver becomes a slave transmitter. Otherwise, the master functions as master transmitter
continuously.
Before the data exchange, Core must check if the bus is used by other masters by reading the status register(stat_r).
If the bus is not used, the address of the slave with which you want to communicate should be written to transmit
register(tx_r), and configure the control register to start the cycle. After interrupt happens, confirming the bus is
acquired and called slave is responded. When the slave is not responded, the sequence must be ended by stop
condition by configuring control register(ctrl_r). If bus is lost and called address is not master itself, I²C block is
gone to initial state. But if bus winner calls this master, master is gone into slave mode. If all these processes are
okay, then the data transfer follows. Data transfer cycle are started by writing transmit register(tx_r) and
configuring control register. When the I²C controller functions as a receiver, tx_r is written with 0xFF. Detailed
sequence is described below.
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