GDC21D601 Datasheet, PDF (177/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
PMU Registers (@0xFFFF F000) -- Continued
ABBREVIATION
BCLKMSK_RUN
BCLKMSK_PD
REMAP
PCLKCR
ADDRESS
0xFFFFF008
0xFFFFF00C
0xFFFFF010
0xFFFFF014
DESCRIPTIONS
BCLK Masking controls register in the
RUN mode.
Enable / Disable clock : 1/0
Bit 15-13 : Reserved
Bit 12 : APB Bridge clock control
Bit 11 : BUS Controller clock control
Bit 10 : DRAM Controller clock control
Bit 9 : DMA Controller clock mask bit
Bit 8 : TEST Controller clock mask bit
Bit 7 : SRAM clock mask bit
Bit 6-1 : Reserved
Bit 0 : B_CLK Out mask bit
BCLK controls register (PD mode.)
Enable / Disable clock : 1/0
Bit 15 : ARM7TDMI Core clock control
Bit 14 : AMBA Arbiter clock control
Bit 13 : AMBA Decoder clock control
Bit 12 : APB Bridge clock control
Bit 11 : BUS Controller clock control
Bit 10 : DRAM Controller clock control
Bit 9 : DMA Controller clock control
Bit 8 : TEST Controller clock control
Bit 7 : SRAM clock control
Bit 6-1 : Reserved
Bit 0 : B_CLK Out control
REMAP register
PCLK control register
Bit 7-3 : Reserved
Bit 2-0: PCLK selection
000 : PCLK = external PCLK source
001 – PCLK = SCLK / 2
010 – PCLK = SCLK / 4
011 – PCLK = SCLK / by 8
100 – PCLK = SCLK / 16
101 – PCLK = SCLK / 32
110 – PCLK = SCLK / 64
111 – PCLK = SCLK / 128
R/W INITIAL VALUE
R/W 16h’FFFF
R/W
16h’0000
R/W
8h’00
R/W
8h’00
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