GDC21D601 Datasheet, PDF (86/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
5. Interrupt Controller Register Descriptions
The following registers are provided for both FIQ and IRQ interrupt controllers:
(1) Mask Register
Readable and Writable. The interrupt mask register is used to mask the interrupt input sources and defines which
active sources will generate an interrupt request to the processor. If certain bits within the interrupt controller are
not implemented, the corresponding bits in the interrupt mask register must be masked. A bit value 0 indicates that
the interrupt is unmasked and will allow an interrupt request to reach the processor. A bit value 1 indicates that the
interrupt is masked. Once a bit is masked, the corresponding bit in the status register is cleared. On reset, all
interrupt input sources are masked.
‘1’ : Mask
‘0’ : Unmask
Initial value : 0x3FFFFFF
25
0
11111111111111111111111111
(2) Trigger Mode Register
Readable and Writable. The interrupt trigger mode register is used to configure the interrupts with the interrupt
trigger polarity register. Each interrupt can be configured to level or edge triggered. A bit value 0 indicates that the
interrupt is configured to edge triggered and a bit value 1 indicates that the interrupt is configured to level
triggered. On reset, all interrupt input sources are configured to edge triggered.
‘1’ : Level Trigger Mode
‘0’ : Edge Trigger Mode
Initial value : 0x2000000
25
0
10000000000000000000000000
87