GDC21D601 Datasheet, PDF (153/189 Pages) Hynix Semiconductor – 32-Bit RISC MCU

GDC21D601
7. I²C Module Signal Description
The I²C module is connected to the APB bus. Table 1. Signal descriptions describes the APB signals used and
produced, Table 1. Signal descriptions shows the non-AMBA signals from the block.
NAME
BnRES
PA[3:2]
PD[7:0]
PSTB
PWRITE
PSEL
TYPE
I
I
I/O
I
I
I
Table 1. Signal Descriptions
SOURCE/
DESTINATION
Reset Controller
APB Bridge
APB Peripherals
APB Bridge
APB Bridge
APB Bridge
DESCRIPTION
ASB soft reset signal (active LOW).
This is part of the peripheral address bus, and is used by the
peripheral for decoding its own register accesses.
The addresses become valid before PSTB goes to HIGH and remain
valid after PSTB goes to LOW.
This is the part of the bi-directional peripheral data bus. The data bus
is driven by this block during read cycles (when PWRITE is LOW).
This strobe signal is used to time all accesses on the peripheral bus.
The falling edge of PSTB is coincident with the falling edge of BCLK
(ASB system clock).
When this signal is HIGH, it indicates a write to a peripheral, when
this signal is LOW, it indicates a read from a peripheral.
This signal has the same timing as the peripheral address bus. It
becomes valid before PSTB goes to HIGH and remains valid after
PSTB goes to LOW.
When this signal is HIGH, it indicates the SSPI module has been
selected by the APB bridge. This selection is a decode of the system
address bus.
Name
SDAin
SDAout
SCLin
SCLout
I²CIRQ
Type
I
O
I
O
O
Table 2. Specific Block Signal Descriptions
Source /
Destination
PAD
PAD
PAD
PAD
Interrupt
Controller
Description
Serial data input.
Serial data output.
Serial clock in
Serial clock output
Active HIGH Interrupt Request
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